ATGEN® software automatically generates high coverage functional test vectors for all types of Programmable Logic Devices (PLDs), including PALs®, FPLAs, FPGAs, FPLSs, and other architectures. These vectors are applied after programming, on a programmer or in-circuit board tester. Testing PLDs individually prior to functional board test or system test results in large savings in testing, diagnosis, repair, and inventory costs. This product is one of a family of ATG products for PLDs that meets the needs of electronic equipment manufacturers and their suppliers in all areas of PLD testing.
This S25 FASTpass product is an effective low-cost generator for customers who want fast test generation of simple tests which will detect the most common assembly related defects.
No fixed limit - depends on host computer resources
Fast generation of short tests to detect catastrophic failures (blank devices, wrong orientation, wrong device, etc.), primarily at board test.
Expedient: Critical-path backtrace technique for shallow circuitry
Ideal for detecting the following common board test defects: unprogrammed parts, part in backwards, wrong part/mislabeled part, catastrophic device failure, numerous open pins
Component testers, translators available
In-circuit board testers, translators available
1 year telephone support
1 year software updates
Functional, no preload
Automatic race detection and repair
Automatic conflict detection and repair on bidirectional pins
Menu and fill-in-the-form interface
Generate equations from JEDEC file in pin-number format
Utility to generate detected & non-detected fault lists
Pinswapping utility to convert vectors between DIP & LCC pinouts
User controllable options
Maximum number of vectors
Maximum burst size
Use vectors from source JEDEC file?
First vector # to use
Use C and K in vectors?
Mark unknown state with X, F, N
Verbose print to screen?
Clock format: non-return, return-to-zero, mixed
Vector minimization: low, moderate, maximum
Tri-state testing: none, pull-high, pull-low, midband
Initialization, 4 options: unknown, powerup low, powerup high, seed vectors
Possible detects optimally analyzed in fault simulator?
Expect state reduction, 2 options: all cares, detects only
Fault classes, 6 settings: pins, logic, logic+intact, logic+intact+blown, Mil454,
Bidirectional pins, 7 settings controlling transient and settled state I/O contention prevention
Type of test, 6 settings: functional, functional+DC, functional+DC+AC, in-circuit board, device+board, custom details
Pins constrained: tied high, low or together, or not fixtured. Output and bidirectional pins may be joined.
FASTpass Mode achieves faster throughput if run time is critical
Simulation & fault grading
Event-driven, time-based algorithms
Concurrent fault simulation
Fault classes: pins, logic, intact fuses, blown fuses
Most up-to-date vector minimization
Credit for original purchase price or current list price (whichever is less) towards higher priced products if Technical Support Service is current.
386 (or higher) MS-DOS or Windows NT PC with hard disk and parallel port; VAX/VMS; Alpha, Sun4, Solaris 1.0 &2.3, and SPARC running Sun OS; HP9000/700 running HP-UX
Signed license, Parallel port key
High software development rate -- small releases every 3-6 months, major releases every 6-12 months.
Latest technology, active engineering
Most suitable for circuitry that is relatively shallow
Generate models for whole-board simulators, such as Teradynes LASAR6 and GenRads HILO. Translators to all popular device, board and AC testers (See separate translator document.)