The Stages of Implementing Boundary Scan Testing
Why haven’t the potential benefits of boundary scan (JTAG, 1149.1) testing been realized yet by a large part of the electronics industry, even though it has shown great promise for many years? Because implementing boundary scan testing is more difficult than is first apparent. A few tools – the right tools – can make a big difference in achieving a successful boundary scan implementation.
Many electronics manufacturers have already embarked on this implementation, but are in the early stages. Companies migrating from in-circuit board testing (ICT) to boundary scan typically go through several stages. Let’s look at what’s involved in a potential migration from traditional bed-of-nails ICT to a hybrid boundary scan/ICT method and ultimately to replacing ICT equipment with low-cost boundary scan test equipment.
Progressive Stages of Boundary Scan Testing
Single-Chip Boundary Scan Tests
As a first step, test engineers use the boundary scan pins on a large device to create an in-circuit test for that device. Common challenges encountered at this single-chip stage are:
• The designer may have hard-wired the boundary scan control pins to power or ground.
• Lack of a low-cost single-chip boundary scan tool and insufficient experience and knowledge to make a wise purchase of a high-end, whole-board, boundary scan test generator.
• Constraints imposed by surrounding circuitry on the board often require modification to data files that drive the test generator in order to make the test work. Modifying these data files is tedious, error-prone, and requires knowledge that the typical test engineer does not have.
Whole-Chain Boundary Scan Testing
After the single-chip stage, enterprising test engineers graduate to attempting whole-chain boundary scan testing. Whole-chain testing involves controlling multiple devices from one 4-pin boundary scan bus on the board. This stage is much more challenging, for several reasons:
• Disabling (guarding) is no longer the sole responsibility of the traditional in-circuit board test software. The whole-chain boundary scan test generator needs to work together with ICT disabling in order to achieve a reliable test. Some tools have trouble in this area.
• The more devices in a chain, the more likely the test will not work the first try because of an error in input data to the test generator. Our experience indicates that perhaps as many as 20% of BSDL files contain errors. With this error rate, a 5-device chain has only a one in three chance of working. (A BSDL file describes the boundary scan logic inside a device.) BSDL files typically are provided by IC manufacturers on BBS and WWW sites at no charge, and with big disclaimers regarding accuracy and support.
• Debugging chains is tedious at best and very difficult at worst, because of the large number of vectors in the test. Successful debugging requires a good understanding of boundary scan operation, which is knowledge few of today's overworked test engineers have had the luxury to acquire.
Pin Reduction
After becoming proficient at whole-chain testing, the natural next step is pin reduction. If all devices on a net contain boundary-scan capability, connecting an ICT pin to the net is not necessary. If all of the chips on a board are boundary-scan-capable, large numbers of ICT pins can be eliminated. Unfortunately, very few boards today contain exclusively boundary scan devices. One solution involves testing non-scan devices through adjacent scan devices. All high-end boundary scan test generators are capable of applying vectors to these non-scan areas of the board, via the scan chain, but users must supply the vectors. Manual vector generation for these non-scan devices is practical only for small devices. Larger devices or clusters of non-scan devices require an additional test generation tool.
Whole-Board Testing
The next stage after whole-chain boundary scan testing with pin reduction is whole-board testing where no in-circuit board tester is used. Very few companies appear to have reached this stage, so we do not know all of the challenges likely to be encountered. It does appear that relying solely on boundary scan testing places additional burdens on designers to provide extra boundary scan access to non-digital components such as resistors, capacitors and connectors. Alternately, faults involving passive components could be tested on a low-cost MDA.
Although there are numerous challenges that must be overcome before the great promise of boundary scan testing can be realized on a widespread basis, the good news is that solutions to these problems have recently become available from ACUGEN® Software, Inc.; knowledge among test engineers is gradually increasing; and competition is heating up to provide more effective tooling at reasonable prices.
Benchmark ACUGEN’s Boundary Scan Tools Now
The new ACUTAPTM tool set addresses many of the challenges faced by test engineers implementing boundary scan methods, so ACUGEN tools can speed up and simplify your transition to boundary scan testing at each stage. ACUGEN Software offers a benchmark with your own file free of charge, so you can see for yourself how these boundary scan test tools can meet your needs.
Benefits
of migrating to boundary scan fall into these broad categories:
1) Reduced cost of test development: Boundary scan testing has the potential to reduce test development costs (since high coverage tests for assembly defects are automatically generated) and simplify test fixtures with fewer pins.
2) Increased fault coverage of assembly defects when used in conjunction with bed-of-nails ICT.
3) Fewer constraints on product design imposed by test: Compared to bed-of-nails ICT, boundary scan testing permits higher density board designs. Higher density is a key driver in several industries (e.g., portable communications and computing), where the potential economic benefit of using boundary scan is huge.
4) Reduced test equipment cost if the in-circuit tester can be replaced by a low-cost boundary scan tester.