AALCA Software automatically converts qualified XILINX designs into simulation models for use by ATGEN® test generation software. This preprocessor product, when used in conjunction with an ATGEN test generator, allows high coverage vector generation for popular LCA devices manufactured by either XILINX or AT & T.
Save time when testing XILINX LCA devices
XC2000, 3000, 4000, and 7000 devices are powerful and complex PLDs, best thought of as small gate arrays. Their flexibility and large size makes manual test development painful and time consuming. The AALCA and ATGEN software automate the test development process, thereby providing major time savings. ACUGEN® ATE translators are also available to produce component and in-circuit test programs, including automatic generation of digital guarding conditions for in-circuit board tests. We estimate the payback of AALCA software to be 1-4 designs, depending on the size.
Two Approaches Available for Higher Quality
The AALCA program can convert the designer's actual netlist into an ATGEN model or synthesize a new design with the same pin usage as the designer's design. While using the designer's netlist theoretically yields a better test, high coverage is not guaranteed because of potential testability and circuit complexity issues. The synthesized model approach produces very high pins stuck-at fault coverage every time, with much shorter run-times and shorter tests. For customers who want the best test possible, we recommend choosing the test that best suits your company's test goals.
The ACUGEN model representation models the logic inside each low level macro using the fewest possible ATGEN primitives (boolean gates, D-latch, tri-state gate, etc.). The macros are connected as specified in the .XNF file.
The AALCA translator produces models that support PINS, LOGIC and MIL454 fault classes. Fuse faults are not supported primarily because the .XNF file contains no fuse information.
Technical Support Service
Technical support and updates are provided in the same manner as your ATGEN base product.
Easy to Use
The translator is invoked by typing "AALCA", followed by the name of the design, at the operating system prompt. If you want manual entry of pin usage for a synthesized model, a convenient fill-in-the-form interface is available.
FASTpass Version Available
For users wanting a fast and low-cost solution well suited to test for the following common board test defects: unprogrammed parts, part in backwards, wrong part/mislabeled part, catastrophic device failure, and numerous open pins, this product is tailored to shallow designs (sequential depth 10). It is a quick check only. For those customers who need high coverage fault detection typical of our Premium ATGEN test generators, the Premium levels of pre-processors are the better choice.
Interface to Design
The designer's netlist comes from the .XNF file without "CLB" or "IOB" information. For the synthesized model, pin information can be entered manually or automatically extracted from the .LCA file. Both the .XNF and .LCA files are readily obtainable from the designer.
To use the designer's netlist, the correct AALCA .XNF file can be created using this command:
LCA2XNF -gut <designname>.LCA
on the computer where the XILINX development system resides. <designname> .LCA must be a fully "placed" and "routed" .LCA file. If you only have a .XNF file with "CLBs" and "IOBs," please ask your designer to perform the following steps to create the correct .XNF file for you:
1. XNFMAP <design>
2. MAP2LCA <design>
3. APR -j <design> <des_new>
4. LCA2XNF -gut <des_new>
<design> = the file name of your original .XNF file (with CLBs and IOBs).
<des_new> = a new name of <design> so the original .XNF file is not destroyed by LCA2XNF. Please use the LCA2XNF V4.34 or later from Xilinx.
Comprehensive Device Support
All XC2000, XC3000 and XC4000 series devices are supported by the synthesized models approach. Support for the designer's netlist is staged in several levels depending on the size of the device.
Requirements -- AALCA
AALCA software must be run on a computer that has an ATGEN S25, S55 or S60 base product installed, and this base product must be maintained up to the latest revision at the time of initial AALCA
purchase. The host computer should have at least 4MB of RAM to run synthesized designs and at least 16MB of RAM for processing designer's designs. These devices have critical CPU speed and memory requirements. See attached Memory Chart for recommendations.
You will need an S55 or S60 version of ATGEN software to run the Premium versions of this software, and an S25, S55 or S60 version to run the FASTpass versions. (Access to the Xilinx Development System is essential for the Synthesized Approach.)
.XNF files from XILINX XACT Development System are used to produce the netlist for the designer's final design. Presently, AALCA software will not generate tests for devices which use the internal tri-state capability of the XILINX devices or which use significant amounts of RAM structures in the XL4000 family. AALCA does not use the Boundary Scan built into the XL4000 family.
The LCA must be loaded with the configuration for the AALCA test vectors to work. AALCA software will not load/configure the LCA-SRAM for you. Tools and documentation are provided with this product to help directly load the configuration into the LCA on the tester in some situations. The tester must have large vector depth and a LOOP UNTIL capability and the LCA's control pins must be accessible to the tester. Talk to an ACUGEN applications engineer for more specifics.
Success Rate for Premium Versions
Due to the potential complexity of Xilinx devices, no software can be guaranteed to reach high coverage on 100% of designs. We recommend that SHARPEYE testability analysis software be used during design to enhance testability. If SHARPEYE software is used and reports no problems with the testability items recommended by us, then we expect our success rate to be 90% on designs with fewer than 100 memory elements and 80% on designs with more than 100 memory elements. A 80% success rate means ATGEN software will detect 90% of detectable gate output stuck-at faults and 100% of pin stuck-at faults on 80% of a typical mix of designs. Note that even an 80% success rate will put you way ahead of writing all tests manually.
Our policy of requesting users to send us designs that attain low coverage has allowed us to make major improvements in our software over the past few years, and we expect the success rate on these Xilinx devices to continue improving.
The testability items we recommend be checked are:
sequential depth less than 500,
no feedback-memories that interact with any other memories,
all clocks, sets, resets controlled by external pins,
no gated clocks,
combinatorial tri-state enable control on outputs